In reply to hsam:
All UVM phases are defined as virtual methods. When run_test() eventually gets to calling the reset_phase of every created component, as with any virtual method, it calls the most derived method for that class object. So unless main::reset_phase calles super.reset_phase, reset_sequence_1 will not get started.
In reply to dave_59:
what will happen if the task reset_phase in base test is not declared as virtual but the main test has declared the task reset_phase as virtual?
In reply to hsam:
Assuming your base_test is extended from uvm_test, which is extended from uvm_component, the reset_phase method (and all other UVM phases) are defined as virtual methods in the uvm_component base class. SystemVerilog rules say that once a method gets defined as virtual, it remains virtual in all other derived classes; the virtual keyword becomes optional.
run_test creates the test and starts executing the phases right, but after create the environment in test it new to the env then how it again call the build phase of test?
run_test() creates the test component and then calls the test’s build_phase(). The test::build_phase() creates children of the test, like the env class. After the test::build_phase finishes, it calls the build_phases of all the child components of the test, which would include the env component. It does this recursively until there are no more children.