Hi Dave, Who Calls the build phase of each components in UVM hierarchy?

In reply to tfitz : The build_phase() method for each component is called top-down by the UVM “root”. What actually happens is that run_test() causes the uvm_test object to be created, then it’s build_phase() is called. The test’s build_phase causes the uvm_env to be created, which adds it to the …

In reply to hoalu : The build_phase is a function, executed in 0 time. If a or b is constructed first doesn’t matter and it might depend on th eimplementation in the simualator.

In reply to chr_sue : Why does it depend on simulator? I think the order here is important and it being handled by UVM? In UVM, it traverses to build a, all sub components of a (topdown order of a tree) then b and all sub components of b.

In reply to chris_le : My understanding is different. Topdown means starting on the toplevel it goes down, creating all components on a certain level and the proceed going to the next level. Then it does not matter if ‘a’ iss constructed first or ‘b’.

In reply to chr_sue : No, UVM build component using “pre-order of a tree traversal” (top-down). [image] From the parent component F, it traverses to build in order: B, A, D, C, E, G, I, H component (source picture from wiki) [image] EDA Playground Edit, save, simulate, synthesize Syst…

In reply to chr_sue : I think it doesn’t matter for the case when there are multiple instances to be created at the same level , so in the above given case whichever is created first (a or b) doesn’t matter. So for all same level in the hierarchy whichever is created fisrt doesn’t matter .

In reply to chris_le : This is exactly why there is a separate connect_phase() in UVM. During build_phase(), the exact order of building doesn’t matter. The point is that, starting with F in your diagram, its build_phase() method will create B and G. Note that these two uvm_components are effectivel…

In reply to tfitz : Thanks for clarifying. In fact, the parent component adds its children to associate-array by name, and the created order can be predictable: class F extends uvm_component; B b_m; G g_m; virtual function void build_phase(uvm_phase phase); g_m = G::type_id::create("g…

In reply to chris_le : The fact that your current UVM implementation creates components in a predictable order does not change the fact that you should NOT rely on components being created in any particular order. With the standardization of IEEE 1800.2, much of the internals of UVM ARE no longer di…

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Calling of build phase?

UVM

cuonghle August 3, 2018, 6:44pm 17

In reply to tfitz:
Hi Tom,
Noticed, thanks for detail explanation.