Calling a class function from inside an always block

SystemVerilog
1

I have module in my testbench. When I call a function inside a class that returns a value I get a build error

Error-[IDTS] Ignoring dynamic type sensitivity
Dynamic types used in always_comb, always_latch, always (@*) will be ignored
for the inferred sensitivity list.

module mo (
a,
b,
c
);

input a;
input b;
output c;

reg c;
foo_t foo;

initial begin
 foo = new();
end

always@(*) begin
  c= foo.bar(a,b);
end

endmodule

class foo_t

function bar (bit a, bit b)
    return a&b;
endfunction

endclass

I do not get this error when I do

c = foo.bar(a,b);

outside the always block and not declaring c as reg

2

It looks like the tool does not allow you to use the always@(*) in this case. Try changing your code to:

always @(a or b) begin
  c = foo.bar(a,b);
end

Hope that works for you. I think foo is the dynamic type the error msg is referring to.

-Ed