Call to other module task with struct as argument

This is my project with 3 files: test bench(tb_test_struct.sv), dut(test_struct.sv) and include(tst_struct_inc.svh)

tb_test_struct.sv


`timescale 1ns/1ns

`include "tst_struct_inc.svh"

module tb_test_struct;
    tst_t abc;

    test_struct t0();

    initial begin
        #100;
        $display("tb");
        abc.a = 33;
        t0.printi(abc.a);
        t0.prints(abc);
    end
endmodule: tb_test_struct 

test_struct.sv


`timescale 1ns/1ns
`include "../tb/tst_struct_inc.svh"
module test_struct();
    task printi(int ivar);
        $display("ivar=%0d", ivar);
    endtask: printi

    task prints(tst_t svar);
        $display("svar.a=%0d", svar.a);
    endtask: prints

    initial begin
        $display("Run test_struct");
    end
endmodule 

tst_struct_inc.svh


`ifndef TEST_STRUCT_INC_SVH
`define TEST_STRUCT_INC_SVH

typedef struct {
    int a, b, c;
} tst_t;

`endif 

Compilation with questa is ok but with 1 error in simulation:
“# ** Error: tb_test_struct.sv(17): (vopt-13216) Arg. ‘svar’ of ‘prints’: Illegal assignment to type ‘test_struct_sv_unit::struct tst_t’ from type ‘tb_test_struct_sv_unit::struct tst_t’: LHS and RHS types do not match.”

From what I understand, for the compiler, the structs tst_t in tb_test_struct.sv and test_struct.sv are different (different “unit”).

How is the right way to call a task (in different module) passing a struct as argument?.

In reply to Peio:

Put typedefs in a common package and import the package into both modules.

See SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons