I am little confused after reading 9.3.4 Block Name and 9.3.5 Statement Labels from 1800-2012.
In that they have mentioned, both have same purpose so why they are differentiate in block and statement, Is there any specific reason to use statement lebel istead of block name. Till now I always use block name.
vcs is still not recognising statement label while ncsim is working fine with below code…
initial begin
begin : block_name
$display(“This is a block_name_bg1”);
end : block_name
statement_name :begin
$display("This is a statement_name_bg1");
end : statement_name
When in comes to begin/end or fork/join blocks, there is absolutely no difference between the two forms.
Statement labels in SystemVerilog are supposed to replace block names in Verilog. But it is extremely hard to remove anything from an existing standard.
Statement labels are useful in reporting and debugging so that you have a label associated with a single statement instead of a filename/line number without having to wrap it in a begin/end block. It also gives your code visibility into the variables declared inside a for/foreach loop.
label: statement
is equivalent to
begin: label statement end : label
except in the case where that statement happens to be a begin/end or fork/join, there is no need for the compiler to insert an extra begin/end.