Block level Verification

UVM
1

Hello Seniors,

i have one dabout suppose in any design there is 5 submodule in design and all 5 submodule instantiated in top module of Design.

than in verification top module we need to instantiate only top module of design or all 5 submodule also.

2

In reply to uvm_verification:

I assume, the top module design specification says that module has 5 sub module instance.
Then top module verification means verification of top module with all 5 sub module instantiated.

3

this is not my answer sir,
i am asking in top module of testbench what we will instantiate top design or or all 5 submodule.

example :-//////////////// Verification top modele

module testbench_top();

top_design();

OR
sub_module1();
sub_module2();
sub_module3();
sub_module4();
sub_module5();
endmodule

4

In reply to uvm_verification:

For me both are same as long as there is no functional requirement that sub_modules have connection in between them.

But if there is some connection between sub_modules then it becomes top level functional requirements which has to be implemented by top level design and then top level design has to be verified. But here I am talking about general design verification flow and your need may be different.