Bitwise toggle coverage for a bitvector

SystemVerilog
4

In reply to nisreenj:

Dave,

I would like to use this approach inside a class, but if I understand your example correctly the covergroup declaration cannot be embedded in the class. How do I create something similar inside a class?

Pseudo code:

class my_coverage extends uvm_subscriber #(apb_seq_item);
:
covergroup output_en_cg (input bit position, ref bit vector);
  encoding: coverpoint (('1b1<<position & vector) !=0)
              {
               bins hit = {1};
               }
               option.per_instance = 1;
endgroup: output_en_cg

output_en_cg g1[16];
:

function new(string name = "my_coverage", uvm_component parent = null);
  super.new(name, parent);
  foreach (g1[i]) begin
    g1[1] = new(i, output_enable_reg[15:0]);
  end
endfunction
endclass

My example code doesn’t compile (no surprise). Ideas?