Bitwise toggle coverage for a bitvector

SystemVerilog
30

In reply to dave_59:
Thanks for sharing the solution. The problem with maximum_width is that simulator expects an equivalent type for ref formal ‘vector’ (ie. Questa will return error 8282).

However, one can override built-in sample method:


covergroup cgmaskbit(input bit [31:0] position) with function sample (bit [MAX_WIDTH-1:0] vector);
  pos: coverpoint (position & vector) !=0;
  option.per_instance = 1;
endgroup