In reply to albert:
You still have not explained your situation very well. Functional coverage in SystemVerilog works by creating in set of value bins associated with a coverpoint, and a set of coverpoints or grouped within a covergroup. The bins are set up once during the covergroup’s constructor. The the covergroup repeatedly samples the values of the coverpoint, and the matching value bins are incremented with hits. You call sample() repeatedly hoping the every bin gets hot.
You need to explain what value will be repeatedly sampled and compared with the predefined set of bin values. Perhaps you need to show an example set of data that would be sampled, and explain which bins would be hit those values.