Bitwise or

SystemVerilog
1

hi,
is it legal to bitwise OR (|) between a single bit and a Boolean expression? will it give me the same as using logical OR (||)?
like so:


if (a | (b==2'b11))
...
...

thanks

2

In reply to gidon:

It’s always legal to bitwise or integral expressions. Whether it gives you the results you want depends on your intent.

The resulting width of equality or relational expressions is 1-bit, so there is no difference between the bitwise or logical OR in this case.