Bitwise and of array,array reduction operator

SystemVerilog
1

i am trying to assing bitwise and of array to single bit wire

 wire [3:0] mpu_region_vr0       = `MPU_PATH.mpu_region_v_r;///rtl path
 wire      mpu_region_vr             =mpu_region_vr0[0] & 
                                      mpu_region_vr0[1] & 
                                      mpu_region_vr0[2] & 
                                      mpu_region_vr0[3] ;

i tried with the function .and() as well still am getting same error is it tool related issue?

i am getting
Incompatible unpacked dimensions in assignment
Arrays with incompatible unpacked dimensions cannot be used in assignments,
initializations and instantiations.

2

In reply to abhineet2210:
There are no unpacked dimensions in what you have shown. What is the declaration for mpu_region_v_r?

This should have worked:

wire mpu_region_vr = &mpu_region_vr0;
3

In reply to dave_59:

reg mpu_region_v_r [`REGION_RANGE];

still getting the same error

4

In reply to abhineet2210:

mpu_region_v_r is an unpacked array that you are trying to assign to mpu_region_vr0, which is a packed array. If the bits line up you can use the streaming operator for unpacked-to-packed array conversion.

wire [3:0] mpu_region_vr0 = {<<{`MPU_PATH.mpu_region_v_r}};