$bits Usage

SystemVerilog
1

`define abc(Bus,Enb,Data)
assign (strong1,highz0) = Bus = En ? Data : {$bits(Bus){1’bz}};

What does this statement mean ?

2

{n{expr}}

means create a concatenation by repeating the expression n times. $bits(Bus) is the number of packed bits of the data type of Bus.

You can simplify this expression with

assign (strong1,highz0) = Bus = En ? Data : 'z;

'z, '0, '1, and 'x are all extended to the proper width based on the context of the assignment target. In this case, Bus.

3

In reply to dave_59:

Hi Dave,
Is the $bits() a runtime function or parsed at compile/elab time? Can I use it in a parameter definition? For example:

logic [$bits(in_header.set_get_hdr.num_word32)-1:0] wr32_remain;

It seems to compiled OK, but not sure if it works similar to the $clog2()?

Thanks,
Richard

4

In reply to hctseng:

Yes, as long as the argument to $bits is a fixed sized type, you can use it as a constant expression.

5

In reply to dave_59:

Thank you Dave!