Bit slicing

SystemVerilog
,
1

Hi,

How to print the 16’hBEEF in 32’hBEEF_CAFE. I tried with the below example,but it is printing 16’hCAFE only. Kindly suggest.

module test();
 
  logic [31:0] data[] = {32'hBEEF_CAFE};
  logic [0:3] re[];
  logic [4:7] im[];
  logic [8:11] pi[];
  logic [12:15] po[];
  
 
  initial begin
    re = new[data.size()];
    im = new[data.size()];
    pi = new[data.size()];
    po = new[data.size()];
  
    
    for(int e =0;e<32;e++) begin
    {im[e],re[e], pi[e], po[e]} = data[e];
  end
    $displayh("im = %p", im);
    $displayh("re = %p", re);
    $displayh("pi = %p", pi);
    $displayh("po = %p", po);
    
  end
 
endmodule
2

In reply to sunils:

use streaming operator to get your answer.

for(int e =0;e<32;e++) begin
{>>{im[e],re[e], pi[e], po[e]}} = data[e];
end

3

In reply to sunils:

What are you expecting it to print?

4

In reply to dave_59:

Hi Dave,

In the above code given, i am expecting that it will print BEEF only, but it is printing only CAFE. Since i am simply using no operator so, that’s why i am expecting it to print BEEF only.