Bit signed - error

SystemVerilog
, ,
1

Hello,

I need to constrain the contents of an array with values ranging from -3 to 3 (-3, -2, -1, 0, 1, 2, 3).

When I do this:

rand bit [1:0] signed my_arr[6]; //error stating "signed" is not expected.

If I do:

rand int my_arr[6];

and follow it with a constraint stating that the values of each array item must be between -3 to 3, I am good. No errors. Why does “bit [1:0] signed” throw an error? Can someone please let me know what I am missing here?

2

In reply to Verif Engg:

A quick search would have told you that the ‘signed’ keyword comes before packed dimensions

rand bit signed [1:0] my_arr[6];
3
If you use bit (which is unsigned data-type), if you use signed syntax then might be show 0-0 value. Kindly check and update.

But from my opinion better to use byte syntax -


module top;
  class sample;
    rand byte my_arr[7];
  constraint c1{
    my_arr[0] == -3;
    foreach(my_arr[i])
      my_arr[i] == my_arr[0] + i;  
  }
  endclass
sample s;
  initial begin
    s = new();
    s.randomize();
    $display("%p",s.my_arr);
  end
   
endmodule

Other way is use of pre_randomize for initialisation.