Binding Parameterized Interface to a Parameterized Module

SystemVerilog
,
1

Hi ,
My parameterized interface is defined as :


interface  intf #( parameter  LENGTH = 10 , HEIGHT = 20 );

 logic [ LENGTH-1 : 0 ]  a ;
 logic [ HEIGHT-1 : 0 ]  b ;

 initial  $display(" Within  %m : LENGTH = %0d , HEIGHT = %0d " , LENGTH , HEIGHT );

endinterface

The interface needs to be instantiated within following module :


module  CSR  #( parameter  LENGTH = 10 , HEIGHT = 20 );

 ...........................
 //  We  Need  to  Instantiate  interface  with  the  Actual  Parameters  for  module  CSR  

endmodule

The module CSR is instantiated as :


module  CSR_top  ;
  ...............

  CSR #( 100 , 200 )  csr() ;

endmodule

Now the requirement is to to bind the interface ’ intf ’ to specific instance ’ csr ’ via the top_tb :


module  top_tb ;
  
  //  The  overridden  parameters  to  the  interface  must  be  the  same  parameters  provided  to  instance name ' csr '  i.e  100  and  200 .
  bind  top_tb.u_chip_top.csr_top.csr  intf#( LENGTH , HEIGHT )   intf_inst() ;

endmodule

This does work , however I am confused how is it that there is No error when I write : intf#( LENGTH , HEIGHT )

How does it take the same parameters i.e 100 and 200 as the overridden one in instance : top_tb.u_chip_top.csr_top.csr

2

In reply to ABD_91:

Bind is just a shortcut for having written

module  CSR  #( parameter  LENGTH = 10 , HEIGHT = 20 );
   
 ...........................
 //  We  Need  to  Instantiate  interface  with  the  Actual  Parameters  for  module  CSR  
   intf#( LENGTH , HEIGHT )   intf_inst() ;
endmodule

So the overwritten LENGTH and HEIGHT parameters get passed down into intf_inst.