Binding multidimensional array in design

SystemVerilog
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1

I have a two dimensional array instances of a two dimensional array in design (can be viewed as model of 2D memory array) that I want to access each element of the array from test bench. I am facing issues with using 2D interface port and binding it to each of the instances. I was wondering if anyone have success with such mechanism or any other way to access the array elements.
Thanks in advance.

2

In reply to anacharya:

Can you provide a sample code of what you have tried and what issues your are running into?

3

In reply to dave_59:

Here is the sample code:

Interface definition:
interface mem_if #(int MEM_WIDTH=64,
int MEM_LENGTH=256)
(
logic [MEM_WIDTH-1:0] memory[MEM_LENGTH-1:0]
)

In the test bench:
bind dut.u_des1.u_des2.mem_bank[0].sub_mem[0].mem_wrapper.mem_inst mem_if mem_if_0(.memory(mem_array));

I have 32 mem_bank instances and 32 sub_mem instances.

The elaboration error I’m getting is:
Expression connected to an ‘inout’ port must be collapsible. (in test bench file)

4

Did this ever get resolved?
I have a similar requirement in my bench.