Binding-Module (SVA)

SystemVerilog
,
1

Hello,
If we have a simulation environment contains:
-DUT file called for example “Test Device”, and
-Test bench file called for example “Device_tb”, and
-We should construct a checker which called for example "Top_Checker” based on SVA that will be used to check some properties about the DUT.
I already saw some examples show some ways to bind the checker with the DUT, and then put it in the test-bench. Is there any other methods of how connecting SVA module to design and put them in the test bench, if there is, please an example will be very useful.

Regrads,

2

In reply to msaidi:

Could you please let us know what are example you have seen to connect check to RTL level using “bind”

3

In reply to cool_cake20:

I am sorry for the delay, But the example that i am working on is confidential and i can give any description of it. i just was wondering if there is some better way to bind the checker with the environment

4

In reply to msaidi:

My question is: why not use bind?

Because using any other way, I think, you will change the DUT and that is not usual. You would be solving a problem and, probably, creating another.

5

In reply to lucaskoelho:

Thanks lucaskoelho
i already used binding and it worked properly