In reply to cgales:
What I am actually doing is,
file_SM1.sv
module SM1 ( logic d, e );
endmodule
file_SM2.sv
module SM2 ( logic f, g );
endmodule
file_AM.sv
module AM ( input logic f, g, d, e);
endmodule
filelist.f
file_SM1.sv
file_SM2.sv
file_AM.sv
top_rtl.sv
module M ( logic a, b, c);
wire d, e, f, g;
SM1 sm1_inst(.*);
SM2 sm2_inst(.*);
bind SM2 AM bind_SM2_AM_inst (.f(sm2_inst.f), .g(sm2_inst.g), .d(sm1_inst.d), .e(sm1_inst.e));
endmodule
It does seem to work.
I can see the assertion module being instantiated under the module it is bound to. All signals seem to be toggling fine.
If this is allowed, what does it mean? I can even bind anything to the assertion module and connect some random signals to the assertion module? In practice this is not very useful, but it seems to be allowed.
Repeating the same code but everything is together for better readability.
module SM1 ( logic d, e );
endmodule
module SM2 ( logic f, g );
endmodule
module AM ( input logic f, g, d, e);
endmodule
module M ( logic a, b, c);
wire d, e, f, g;
SM1 sm1_inst(.*);
SM2 sm2_inst(.*);
bind SM2 AM bind_SM2_AM_inst (.f(sm2_inst.f), .g(sm2_inst.g), .d(sm1_inst.d), .e(sm1_inst.e));
endmodule