Bind module allows only simple instance name

SystemVerilog
,
1

Hi:
I write a piece of code like this and receive a elab warning: Warning-[BMAOSIN] Bind module allows only simple instance name.


bind.sv
    bind    xx_crg:tb_top.dut.u_xx0.u_xx_xx   my_checker u_my_checker(
 
        //output
        .clk_out            (clk_vpu_enc)
 
    )

So, if there is a situation where module A has been instantiated 3 times(u_a0/u_a1/u_a2/), and each instance contains a submodule B(u_b), I want to bind my checker to each u_b(u_a0.u_b/u_a1.u_b/u_a2.u_b/), how to use bind to avoid this warning?

2

In reply to jianfeng.he:

What you wrote should have worked, but we would need to see a little more code to be sure.

If you want to bind to all module B’s, you can simply write

bind    B   my_checker u_my_checker(
3

In reply to dave_59:
Sorry, I didn’t explain clearly. What I meant to say is if I want to bind my_checker to one instance of mudule B(for example u_a0.u_b), but this module has been instantiated multiple times with the same instance name u_b(u_a1.u_b u_a2.u_b …), so I write like this:


bind    B:u_a0.u_b   my_checker u_my_checker ...

But this may cause the elab warning: Warning-[BMAOSIN] Bind module allows only simple instance name. So is there any way to avoid this warning while still achieving the above functionality?

4

In reply to jianfeng.he:

Only one tool on EDA playground gives this warning. You will need to contact your tool vendor for additional assistance.