Bind module allows only simple instance name

SystemVerilog
,
1

Hi:
I write a piece of code like this and receive a elab warning: Warning-[BMAOSIN] Bind module allows only simple instance name. What’s the reason?


xx.sv
    interface crg_clk_checker
    #(
        parameter int   CLK_WIDTH = 1
    )(
        //clk output
        input   logic[CLK_WIDTH-1:0]        clk_out
    );
        ...
    endinterface

bind.sv
    bind    xx_crg:tb_top.dut.u_xx0.u_xx_crg crg_clk_checker#(.CLK_PERIOD_FREQ_EXP(2)) u_crg_clk_checker_enc(
    
        //output
        .clk_out            (clk_vpu_enc)

    );
2

In reply to jianfeng.he:
Change the bind statement to the following to eliminate the warning:


bind    xx_crg:u_xx_crg crg_clk_checker#(.CLK_PERIOD_FREQ_EXP(2)) u_crg_clk_checker_enc(
 
        //output
        .clk_out            (clk_vpu_enc)
 
    );