Bind interface UVM

Hi everyone
I use bind to connect to a internal interface on my module top_tb:
bind dut.wt_clock_mux_glitch_free wt_clock_mux_if wt_clk_mux_if0(
.clk1(clk1),
.clk2(clk2),
.rst_b(rst_b),
.wt_clk_sel(wt_clk_sel_r),
.wclk(wclk)
);

but I got an error:
Hierarchical name component lookup failed at ‘dut.wt_clock_mux_glitch_free’.
Error during elaboration (status 1), exiting.

I need some advices,
Thank you!