Bind assertion module to different instances of RTL module with different hierarchies

SystemVerilog
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1

Hi,

I am new to using Bind concept.

In the design, there are multiple instances of RTL module (mod3) which are at different hierarchy and for each instance the signals have different port connections.
EX:
Top.mod1_inst1.mod2_inst1.mod3.vld
Top.mod1_inst2.mod2_inst2.mod3.vld

Q1: How can I provide hierarchy names in the bind statement using for loop?
Q2: In my assertion module, should I create a array for the signal vld[2] and connect to each instance of the signal?

Currently I am using just one instance of my assertion module to bind as I want to verify all vld signal from different rtl instances at same time.

I tried to use the generate and endgenerate but it is giving me error that bind cannot be used inside the generate block.
Also, by creating the array, I couldnt bind the signals too.

Please help me with the problem.

Thanks,

2

In reply to jyothsna04:

If there are multiple instances of mod3, you can use bind to insert an assertion module into each instance

bind module3_name assertion_module am_inst(vld);

This creates two instances of the assertion module

Top.mod1_inst1.mod2_inst1.mod3.am_inst
Top.mod1_inst2.mod2_inst2.mod3.am_inst

3

Hi Dave,

Your reply really helped me.

I have another related question:
What if I do not want to bind all instances of the “my_module”?
I want to be able to bind some and leave the remaining but the issue is that the bind statement either expect a complete instance path or it expects only the module name. It doesn’t even accept wildcard ‘*’ so that I can filter.

I have different instances with different parameters and only want to connect a specific sub set of instances.

What will be the best solution. I do not want to write bind statement for each instance separately.

Thanks

4

This is an XY problem.

You must bind each instance individually with the desired parameters. If we knew more about why you wanted to only bind specific instances and not do them individually, we might be able to suggest alternatives.

5

There is an array of instances of the module:
projtop.lane[L].mymodule_top.loop_16[N].mymodule_i0
where each mymodule has different parameters.
In the bind statement I do not need to pass any parameters as the parameters for mymodule are set in the project and paramters in sva file are only defined for the specific parameter values.
I was hoping there was a way where I could do this:
bind projtop.lane[**].mymodule_top.loop_16[2].mymodule_i0 mysva mysva_inst(.*)
or maybe do it in a loop where I could control values of L and N to keep the binding code concise