Bind a vhdl entity to a uvm class

SystemVerilog
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1

Hi
Is there a way to bind a class(a uvm parametrized class) to a vhdl entity,so that every instance of that entity will have an object of that class associated with it?
E.g. suppose I have an entity named “DMA” in my DUT,which instantiated in multiple places in the design,and I wrote a monitor for this entity,which is a class named “DMA_monitor”.
I want every instance of DMA to be binded to an object of DMA_monitor.
An example will be very helpful.
Thanks!

2

In reply to shaygueta:

You can bind a module that has a class object into a VHDL entity. The following examples bind into a Verilog module, but also work the same for binding into a VHDL entity.

https://verificationacademy.com/cookbook/connect/twokingdomsfactory
https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection