In reply to uvmsd:
SystemVerilog has only 1 bind construct. You can use it to observe signals in your DUT and also drive signals if the DUT is written in SV. Binding assertions to your DUT is one application.
In reply to uvmsd:
SystemVerilog has only 1 bind construct. You can use it to observe signals in your DUT and also drive signals if the DUT is written in SV. Binding assertions to your DUT is one application.