In reply to chr_sue:
1.yws. 800 sequences have different address and data for RAM1(writing into all the locations)
2. Yes, control module is a verilog module. I am sending two sequences which would ensure a pulse of trigger(high and low). This value will be set to zero in above 800 sequences.
What you have suggested matches to option 2 of above list. I think I have access to signals of control module through interface. Does the bind you mentioned is similar to bind used in assertions?
Thank you, will look into it.