In reply to uvmsd:
A few questions to get the right understanding:
(1) you have sequence executing WR to RAM1; generates 800 seq_items with different addr and data. Correct?
(2) What kind of component is the control module you are triggering. Is this a Verilog module or is it a uvm_component belonging to your verification environment?
You can obeserve the internals of this control module. If it is a Verilog/SV module you can bind an observing component to the control module counting the numbers of reads and writes. If the reads and writes are complete you can trigger an event which is waited on in the driver and you can continue with your writes to RAM1