Best representation of list of bit in Systemverilog

SystemVerilog
1

Hi,

what’s the best way to represent a list of bit in Systemverilog? I tried the following but I think there is an impact on memory when you deal with large lists.


rand bit lob[];

thank you,

2

In reply to Mohamed_TN:

It would probably be more efficient to define a list of bytes or words. How efficient depends on what you mean by large, and how you plan to access the bits.