Best approach to verify a transceiver

UVM
,
1

I have always struggled with which would be the best strategy for this.

I have learned that there could be different approaches for this:

  1. create first a transmitter reference model, then a receiver reference model, then connect them together and check the input with the output to make sure they match, then connect transmitter rtl with receiver ref model, to verify transmitter, then, connect receiver rtl with transmitter ref model to verify receiver.

  2. verify transmitter rtl using a transmitter reference model, then connect transmitter rtl with receiver rtl back to back (to verify receiver (no receiver model)).

  3. connect transmitter rtl with receiver rtl directly, with transmitter reference model used to receive input of tx rtl and compare with tx rtl output, and in the same env, a receiver reference model to to receive input to rx (output of tx), with output of rx.

so, how do i go on about this? lets assume I have a UART transceiver that needs to be verified.