Behaviour of disabling fork with label across simulators

SystemVerilog
, , ,
1

I am noticing different simulators behaving differently for disable fork with label.
I want to understand the actual interpretation of the IEEE Std 1800-2017, section 9.6 & sub-section 9.6.2.

Here is the sample code.

module disable_fork_check;

  int A;
  int B;
  int C;
  
  initial begin
    fork : CHECK
    // Thread 1
    begin
      forever begin
        @(posedge A);
        if(B == 1)
          $display($time, " B = 1");
      end
    end
    // Thread 2
    begin
      @(C == 1);
      $display($time, " DEBUG :: C = 1");
    end
    join_any
    disable CHECK;
    $display($time, " Disabling CHECK");
  end
  
  
  initial begin
    A = 0; B = 0; C = 0; #10;
    A = 1; B = 0; C = 0; #10;
    A = 0; B = 0; C = 0; #10;
    A = 1; B = 1; C = 0; #10;
    A = 0; B = 0; C = 0; #10;
    A = 1; B = 0; C = 1; #10;
    A = 0; B = 0; C = 1; #10;
    A = 1; B = 1; C = 1; #10;
    A = 0; B = 0; C = 1; #10;
    $finish;
  end
  
endmodule : disable_fork_check

When the above code is executed in Sysnopsys VCS 2019.06 or Aldec Riviera Pro 2017.02 the result was;

30 B = 1
50 DEBUG :: C = 1
50 Disabling CHECK

But, when the same code is executed in Cadence Incisive 15.20, the result was;

30 B = 1
50 DEBUG :: C = 1
50 Disabling CHECK
70 B = 1

Which tool is interpreting the IEEE Std correctly?

2

In reply to thangavelu_bheema:

Majority wins.