Backslash in macros

SystemVerilog
1

Hi SV forum,
Why do we need to add backslash when we write macros
for example:


`define macro_name (arg) \
  begin \
    case(sel) \
       ... ; \
2

Hi shimonc,

The backslash are used in multiline macros.
Which apparently indicates the below line is part of macro.
Last Line in every multiline macro will not have backslash in the end, all other lines must have backslash in the end which is considered as continuation of macro.

For further details in macro, you can visit the following Blog:

Regards,
Dhruvesh.B

3

In reply to shimonc:

Because `define macros are just simple text replacement constructs that replace whatever text until reaching the end of the line. They do not understand SystemVerilog syntax and just insert whatever test that appears on that single line. The backslash-newline is an escape sequence is the only way of telling the macro processor that the macro text continues on the next line.