Although the assign based solution would have worked, I would have needed to add the same assign based logic in SS_top_tb & Complex_top_tb as well
I went ahead with replacing reg_block.TAIL_PTR.read(status,rd_data,UVM_BACKDOOR); with if( !uvm_hdl_read(“tb_top.<RTL_hierarchy>.tail_ptr“,rd_data) ) `uvm_error(..)
Since the RTL hierarchy would vary based on SS / complex based simulations I have 3 calls to uvm_hdl_read based on respective compiler directives.