Backdoor RAL read issue

UVM
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1

Hi,
I’m trying to read (RAL) via BACKDOOR this RW register (40 bits width), after performing a FRONTDOOR write (the FRONTDOOR read works properly):

  uvm_reg       urm_reg[$];
  uvm_reg_field urm_reg_field[$];

  uvm_status_e   dbg_status;
  uvm_reg_data_t dbg_data;

  urm_reg[0] = tb.bus_regmap.get_reg_by_name("urmf_cnt_init_inst");
  urm_reg_field[0] = urm_reg[0].get_field_by_name("urmf_cnt_init");
  urm_reg_field[0].write(dbg_status, 40'hFFFFFFFFFF);
  urm_reg_field[0].read(dbg_status, dbg_data, UVM_BACKDOOR);
  urm_reg_field[0].read(dbg_status, dbg_data, UVM_FRONTDOOR);

(I know that the register will be used instead of field for the backdoor access)


string urmr_cnt_init_path ="if_uc.int_cnt_init";
class urmr_cnt_init extends uvm_reg;
   `uvm_object_utils(urmr_cnt_init )

   rand uvm_reg_field urmf_cnt_init;
                      
   function new(string name = "urmr_cnt_init ");
      super.new(name, 40, UVM_NO_COVERAGE);
   endfunction

   virtual function void build();
      
      urmf_cnt_init= uvm_reg_field::type_id::create("urmf_cnt_init");
      urmf_cnt_init.configure(this, 40, 0, "RW", 0, 'h0, 1, 1, 1);
      add_hdl_path_slice(.name(urmr_cnt_init_path), .offset(0), .size(40));
      
   endfunction
endclass

the regmap is created and the root path added with this line of code:


bus_reg_map = create_map("bus_reg_map", 'h00, 4, UVM_LITTLE_ENDIAN);
bus_reg_map .configure(.hdl_path("top.dut"));

so the access is 4-byte type.

the VHDL signal is defined in such a way:

signal	int_cnt_init : std_logic_vector(39 downto 0) := (others => '0');

The value read is 40’hFFFF000000 (40’hFFFFFFFFFF was expected).
This is very tricky for me, any suggestion?

2

In reply to alexkidd84:

Your
add_hdl_path_slice(.name(urmr_cnt_init_path), .offset(0), .size(40));
is wrong.
It should be like this:

urmf_cnt_init.add_hdl_path_slice(.name("urmf_cnt_init"), .offset(0), .size(40));

and I do not see the

add_hdl_path(...);
3

In reply to chr_sue:

I edited the post, the add_hdl_path is composed by the configure and the add_hdl_paht_slice

4

In reply to alexkidd84:

I do not know what
string urmr_cnt_init_path = “path_to_register”;
is. Because you do not show it.
In general add_hdl_paht_slice is the name of the register as a string as I have shown in my last post.
If your hdl_path is top.dut the registrer is in the toplevel of your design.

5

In reply to chr_sue:

I supposed that name in add_hdl_path_slice contains the HDL register name (not the uvm_regm name) that should be append to the HDL general path.

6

In reply to alexkidd84:

Yes, that’s correct. But you do not set it to this value.

7

In reply to chr_sue:

In reply to alexkidd84:
Yes, that’s correct. But you do not set it to this value.

let’s suppose the entire path is: “top.dut.if_uc.int_cnt_init”. It will be split in two separate path:
root path: top.dut
register path: if_uc.int_cnt_init

8

In reply to alexkidd84:

I did not try this. But you might be right. But it has to be a string. Unfortunately I do not see this.