AXI4- explanation regarding transaction, data transfer, burst and beats

SystemVerilog
1

I’m little confused regarding the relationship between the above concept.

Does burst is just a type of AXI transaction> Can it take more the one clock transaction?

What is exactly a beat? does it contain address and data?

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In reply to saritr:

AXI Burst can consist of variable number of Beats. Burst type AxBURST can be FIXED, INCR, WRAP and in each type number of beats are represented by AxLEN(Burst Data Length). (x is R: ReadChannel/ W:WriteChannel).

Here, as beat transfers depend on handshake between AXI Master/Slave, each beat can take more than 1 clock to transfer. So, AXI Burst also can take more than 1 clock cycle depending on No. of Beats and Handshake process.

A Beat contains Data of size secified by AxSIZE. With each address(AxADDR), set of data beats(AxLEN) to be transfer are associated.