In reply to ben@SystemVerilog.us:
Reset is declared as logic and it is always high.
Yes, pass and fail are added properly.
int pass, fail;
property bresp_valid;
@(posedge clk) disable iff(reset==0)
(bvalid) |-> (bresp == 0);
endproperty
VALID_CHK1:assert property(bresp_valid) pass=pass+1; else fail=fail+1;