In reply to ben@SystemVerilog.us:
I am writing on these registers one after another - awaddr = {1C, 30, 34, 44, 48}
and the bresp for all these writes is 3
Observation after adding above pass/fail variable is that the Assertion only fails for awaddr 1C, 30 and doesn’t pass or fail for other invalid writes (assertion inactive?)
Expectation is that it should fail for all above writes. Please check waveform below and suggest.