In reply to verif_guy12:
Are you sure that this is the cycle where you think the assertion passes instead of failing?
Retry the simulation with the following code and traces.
int pass, fail;
property bresp_valid;
@(posedge clk) disable iff(reset==0)
(bvalid) |-> (bresp == 0);
endproperty
VALID_CHK1:assert property(bresp_valid) pass=pass+1; else fail=fail+1;
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
or Cohen_Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog