Avoiding inferred latches in a combinational circuit

SystemVerilog
,
5

In reply to dave_59:

I thought that since this is a behavioral description, we can describe it just like in C-programming(where this would be acceptable). However, even after having an else/else-if for every if-condition and removing some redundant code, I’m getting the same error again.


module LAB_2(
input logic [3:0]A_m,B_m,
input logic A_s,B_s,op,
output logic Y_s,
output logic [3:0]Y_m
);
always_comb
begin
if(op==1) //addition
	begin
		if(A_s==B_s)
			begin
			Y_m=A_m+B_m;
			Y_s=A_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
			end
			
// When signs are not equal:
		else if((A_m>=B_m)&&(A_s!=B_s))
			begin
			Y_m=A_m-B_m;
			Y_s=A_s;
			end

		else if((A_m<B_m)&&(A_s!=B_s))
			begin
			Y_m=B_m-A_m;
			Y_s=B_s;
			end
	end

else if(op==0) //subtraction
	begin
		if(A_s==B_s) // when signs are equal.
			begin
				if(A_m>=B_m)
					begin
					Y_m=A_m-B_m;
					Y_s=A_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
					end
				else if(A_m<B_m)
					begin
					Y_m=B_m-A_m;
					Y_s=B_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
					end
			end
			
		else 		// if(A_s!=B_s) i.e. when signs are different.
			begin
			Y_m=A_m+B_m;
			Y_s=A_s;
			end
	end
end
endmodule