Avoiding inferred latches in a combinational circuit

SystemVerilog
,
3

In reply to dave_59:

I tried re-structuring the code to include all possible cases(including what you suggested). But I’m getting the exact same error. Is there anything else I can do? The following is my updated code:


module LAB_2(
input logic [3:0]A_m,B_m,
input logic A_s,B_s,op,
output logic Y_s,
output logic [3:0]Y_m
);
always_comb
begin
if(op==1) //addition
	begin
		if(A_s==B_s)
			begin
			Y_m=A_m+B_m;
			Y_s=A_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
			end
// When signs are not equal:
		if((A_m>=B_m)&&(A_s!=B_s))
			begin
			Y_m=A_m-B_m;
			Y_s=A_s;
			end

		else((A_m<B_m)&&(A_s!=B_s))
			begin
			Y_m=B_m-A_m;
			Y_s=B_s;
			end
	end

if(op==0) //subtraction
	begin
		if(A_s==B_s) // when signs are equal.
			begin
				if(A_m>=B_m)
					begin
					Y_m=A_m-B_m;
					Y_s=A_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
					end
				else(A_m<B_m)
					begin
					Y_m=B_m-A_m;
					Y_s=B_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
					end
			end
			
// if(A_s!=B_s) i.e. when signs are different.

		else 
			begin
				if(A_m>=B_m)
					begin
					Y_m=A_m+B_m;
					Y_s=A_s;
					end
				
				else(A_m<B_m)
					begin
					Y_m=A_m+B_m;
					Y_s=A_s;
					end
				
			end
	end
end
endmodule