Avoiding inferred latches in a combinational circuit

SystemVerilog
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2

In reply to VIKRANT97:

Please use code tags to make your code easier to read. I have added them for you.
It would also help to indent your code based on the nesting level of if and begin/end blocks. That I’m not going to do for you.

You avoid latches by making sure there is an assignment to a variable in every possible path though your code. You are missing the case when A_m==B_m. It would be much easer to catch this if you had written your if branches with an else clause rather than two separate if’s.

if (A_m < B_m}
   // code
else
   // code for A_m >= B_m