Hello friends,
I have read many books on verilog and system verilog, and no where it is clearly mentioned that why is it necessary to make function automatic when we use ref keyword. I have swapped two values using ref keyword(passed through module to function )without using automatic and in synopsys simulator(VCS) it is running and swapping the values without error and warning but in cadence ncsim it is showing error.
I have one more doubt can I correlate ref keyword concept same as call by reference in C language. In C the picture is very clear because there we can imagine how memory blocks are created and how swapping is done using pointers’ call by reference but in system verilog I am not able to imagine it.
Can someone also suggest me good book or resources where as a beginner I can clear these types of concept.