Join Academy Subject Matter Expert, Tom Fitzpatrick for the August UVM Recipe of the Month - Automating the Creation of Your UVM Register Model.
Overview:
The UVM Register Layer is a great way to abstract the interaction between your testbench and your DUT from the pin-level, or even protocol-specific transactions to a generic register-based view of communication. This abstraction provides many benefits, not the least of which is isolating your stimulus generation and coverage modeling from low-level changes in your design (i.e. separating the what from the how). Unfortunately, the benefits of using the register layer come at the cost of having to specify the register models in your testbench to reflect the registers in your hardware. With thousands or even tens of thousands of registers in a typical design, this can be a laborious and error-prone process when done from scratch. This UVM Recipe of the Month will introduce the Register Assistant feature of the Questa Verification Platform and show how it can be used to quickly generate correct-by-construction register models and tests from a register specification.
In addition - if you are already an Academy Full Access member, get a head start with Register Models in the UVM Cookbook.
Watch and Learn:
- Brief review of the UVM Register Layer data model.
- Creating a spreadsheet-based Register Specification
- Generating the register model code.
- Modifying your Register Specification.
- Adding Coverage and other advanced capabilities to your register model.