Asynchronous FIFO Multithreaded assertion

SystemVerilog
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7

In reply to ben@SystemVerilog.us:

Thanks Ben for the detailed explanation ,

A clocking event in the declaration of a sequence or property does not flow out of an instance of that sequence or property.
However, the clock flows across elements of same sequence.

So for the following ::


 sequence  s1;
   @( posedge clk0 )  b  ##1  c ; 
 endsequence

 sequence  s2;
   @( posedge clk1 )  d  ##1  e ; 
 endsequence

 sequence  s;
   @( posedge clk )  a  ##1  s1  ##1  s2  ##1 f ; 
 endsequence

’ c ’ is clocked on clk0 , ’ e ’ is clocked on clk1 , ’ f ’ is clocked on clk as the clk1 don’t flow out of the sequence s2

Sequence ’ s ’ is equivalent to ::


 sequence  s;
   @( posedge clk )  a  ##1 ( @( posedge clk0 )  b  ##1  c ) ##1 ( @( posedge clk1 )  d  ##1  e )  ##1 f ; 
 endsequence

Personally I always feel like basics go a long way , so this sure is an important piece of info .