In reply to ben@SystemVerilog.us:
Hi Ben ,
For the multiclocked property ::
(a) If both @(posedge r_clk) and @(posedge w_clk) are True at T0 then
p_rbaddr , p_rdata , p_wbaddr and p_wdata are all assigned at T0.
(b) If @(posedge r_clk) is True at T1 whereas @(posedge w_clk) is False at T1 ,
then p_rbaddr and p_rdata are assigned at T1 and p_wbaddr and p_wdata are assigned at nearest @(posedge w_clk) .
[Q1] Is my understanding correct for (a) and (b) ?
[Q2] When is the consequent evaluated ? i.e which clock is used
Is it at the next @(posedge r_clk) OR next @(posedge w_clk) ?