In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for the reply.
I am using Formal verification to prove this (QuestaFormal). I think EDA playground is simulation based.
This is the error I am getting: line 188: Unsupported subset of multi-clock constructs…
Yes you are correct. In the RTL they used a w_memory based on w_clk and a r_memory based on r_clk. But r_memory is basically w_memory-clock synced to r_clk, ie synced to read out at r_clk. so effectively we can say its one single memory. I am skipping the low level impl code just to keep things simple here.
Thank you