Asynchronous Assertions

SystemVerilog
, ,
6

In reply to Satputesb:
The following works but it has an issue if B and C occur simultaneously because the order of processing of the fork elements is not predictable. Thus if fork2 is processed before fork1 you can get an OK. The concept demoed here may guide you into a better approach.


module m;
    `include "uvm_macros.svh"     import uvm_pkg::*;
  bit A, B, C, run;   
  event t0, t1, ta, tb, tc;  

    /*nLet me re frame the question there are three different "single bit inputs"
    Input A1(Single bit);
    Input A2(single bit);
    Input A3(Single bit);
    
    All these inputs arrive in specific sequence. which
    Fisrt A1 is asserted and kept high. 
    Then after sometime A2 is asserted and kept high. 
    And then A3 is asserted and kept high. 
    These inputs are externally driven. 
    I would like to write assertion for checking if these are being asserted in specific sequence. */ 

    task automatic t_abc; 
        automatic bit a, b, c, oka, okb, okc; // history + status 
        -> t0;  // debug
        fork
            fork1: begin 
                @(A) a=1;
                am_A1_B0_C0: assert(!B && !C && !b && !c) oka=1;
                -> ta;
            end
            fork2: begin 
                @(B) am_A1_B1_C0: assert(!A && !C && a && !c) okb=1;
                b=1; 
                -> tb;
            end
            fork3: begin 
                @(C) am_A1_B1_C1: assert(!A && !B && a && b) okc=1;
                c=1; 
                -> tc;  
            end
        join
        am_ABC: assert(oka && okb && okc);
        -> t1;  
    endtask 

    always @(posedge run) begin
        t_abc(); 
    end

	initial begin 
        bit a0, b0, c0;
		repeat(250) begin 
			#20
            if (!randomize(a0, b0, c0, run)  with 
					{ a0 dist {1'b1:=1, 1'b0:=4};
					  b0 dist {1'b1:=1, 1'b0:=4};
                      c0 dist {1'b1:=1, 1'b0:=4};
                      run dist {1'b1:=1, 1'b0:=15};
					}) `uvm_error("MYERR", "This is a randomize error")
            #5; A=a0; B=b0; C=c0; 
		end 
		$stop; 
	end 

endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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