Asynchronized and Synchronized Assignment to The Same Signal

SystemVerilog
1

Hi all,

I need to asynchronized reset and synchronized drive a signal in my environment. So, I write my testbench similar as the following.

However, I got a 1’bX after the second assignment ( u_test.syn() ). Does anybody have any idea about this? Why does a 1’bX occur? How to resolve this problem?

interface intf ( input clk ) ; wire vdio_poe ;

clocking cb @ (posedge clk ) ;
output vdio_poe ;
endclocking

modport SLV (
clocking cb ,
output vdio_poe
) ;
endinterface

class test;
virtual intf.SLV u_intf ;
function new ( virtual intf.SLV u_intf ) ;
this.u_intf = u_intf ;
endfunction

function void asyn() ;
u_intf.vdio_poe <= 0 ;
endfunction

function void syn() ;
u_intf.cb.vdio_poe <= 1 ;
endfunction
endclass

module tb ( ) ;
reg clk ;
intf u_intf ( clk ) ;

initial begin
clk = 0 ;
forever #1 clk = !clk ;
end

test u_test = new ( u_intf ) ;

initial begin
#10 u_test.asyn();
#10 u_test.syn() ;
end
endmodule

2

It is illegal to allow procedural assignments to a wire; your simulator should have flagged this as an error. Your example is a good illustration of why it should not be allowed.

A clocking block drive to a wire behaves like a continuous assignment from an internal clocking block variable to your output wire vdio_poe. Normally when there are multiple drivers on a wire, you only have one active driver, and all the other drivers are driving a 'z. If you have more than one active driver and they are driving different values, you use the wire resolution rules to come up with a resolved value. Normally, driving a '1 and a '0 simultaneously produces an 'x. But if you allow an instantaneous procedural assignment to a wire, how long is the “assignment” in effect? There is no good answer that generally works.

There are a number of solutions to your problem depending on your actual environment.

You could change the declaration of vdio_poe to a variable instead of a wire, assuming there are no other drivers of this signal.

As in real hardware, you could gate the asynchronous enable together with the synchronous enable inside your interface.