In reply to Andrew R:
// You have 2 clock systems
// Use as sampling clock the slower clock in your consequent,
// but use the negedge of clock to sample the clock signal.
assume property (@(edge mclk) $fell(async_signal) |->
@(posedge clk) (!async_signal throughout ($rose(clock, @(negedge clock))[*3])));
// On the cover, I would use the got operator
cover property (@(posedge mclk) async_signal[->2]);
// goto: a[->1] is same as !a ##[0:$] a
// a[->2] is same as !a ##[0:$] a ##1 !a ##[0:$]a
Ben Cohen
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