Assignment of handles from paper " Yin and Yang of Obj Oriented Verification "

SystemVerilog
,
3

In reply to dave_59:

Have another question about the suggestion to declare the base class value parameter with explicit type , int .


   class  Base #( int PARAM = 10  ) ;  // ' PARAM ' would  ALWAYS  be  int  data  type  .
   endclass

    Base # ( 10 )  b1  ;   




class  Subtype  #( PARAM = 10  )  extends  Base #( PARAM ) ;
endclass

//  Irrespective  of  Specialization  for  Subtype , Base :: PARAM  would  ALWAYS  be  int

Eg  ::  parameter  logic  [ 15:0 ]  LOGIC_16 = 10 ; 

        Subtype #(  LOGIC_16 )  s5 ; 

//  Subtype #(  LOGIC_S16 ) :: PARAM  is  logic  Unsigned  parameter  of  Size  16 

        initial   begin  

         s5  =  new() ;

         b1  =  s5  ;  // This  is  Successful but  how  ??

        end
 



logic  unsigned [15:0] ( Specialization  of  Subtype , s5 )  and  int  data  type  (  Specialization   of  Base , b1 ) are  Not  Matching  types .

However Base #( 10 ) :: PARAM and BASE #( PARAM ) passed via Specialization of Subtype Class ( s5 ) are Matching Types as they are int data type ALWAYS .

Is this why the Assignment is Successful ?