In reply to Etrx91:
I believe you have found a few deficiencies in the LRM. I believe the intent is that class parameter overrides should work the same as module parameter overrides (See section 23.10 Overriding module parameters in the
IEEE 1800-2017 SystemVerilog LRM.
That says overriding an untyped values parameter takes on the type of the final override.
Then section 8.25 say that a class specialization is defied by value parameter when both their type and their value are the same. But it really should to use the matching type rules in section 6.22.1 Matching types.
Unfortunately, I tried this on four different simulators on EDA playground and got four different results with the unsuccessful cases 2 &4.
You can avoid this ambiguity by declaring the base class perimeter with an explicit type.
class Base #( int PARAM = 10 ) ;
endclass