Assigning queues in system verilog

SystemVerilog
,
7

In reply to confused kid:
Here’s what I mean by a complete self-contained example using your original post and adding the necessary code to compile and run it.

module top;
   int h[8]= {1,2,3,4,5,6,7,8}; // I'm assuming these numbers are arbitrary	
   int x[8]= {1,2,3,4,5,6,7,8}; // You never showed this declaration
   int sum;
   initial begin	
      for(int n = 0; n<8; ++n)begin
	 sum = 0;
	 for(int k = 0; k<=n; ++k)begin
            sum += h[k]*x[n-k];
	 end
	 $display(n,, sum); // I added this for debugging
      end
   end
endmodule

And here is the output I get:

# run -all
#           0           1
#           1           4
#           2          10
#           3          20
#           4          35
#           5          56
#           6          84
#           7         120
#  quit -f

Can you show us in C the same thing you are trying to write in SystemVerilog?